A digital-to-analog (DAC) comprises one or more cells, each of which receives a sequence of digital values and outputs an analog signal that varies in response to state changes in the sequence of digital values. Often, a DAC cell comprises a current source and a current source driver.
FIG. 6 illustrates an exemplary one of many conventional DAC cells 600. The DAC cell 600 comprises a current source 604 and a current source driver 602. The current source driver 602 comprises a pair of inverters 606, 608 that receive a differential digital input signal (SEL, SEL). In response to state changes of the differential digital input signal, the inverters 606, 608 cause first and second control signals (VG, VG) to be driven between first and second reference voltages (Voff, Von). As one or the other of the first and second control signals is driven low, a respective one of a pair of current steering transistors 610, 612 is turned on, and current is steered between Iout and Iout.
As shown in FIG. 7, the control signals (VG, VG) are differential, with their edges crossing at or about the average value of the first and second reference voltages. Unfortunately, this produces a large glitch (ΔVx) in the voltage (Vx) at the tail node of the current source 604 (FIG. 6). The glitch can impact both settling performance and linearity of the DAC cell 600.
Various solutions for mitigating or eliminating the voltage glitch (ΔVx) have been proposed. However, these solutions often have other deleterious affects on a DAC cell, such as: undesired charge pumping between the first and second reference voltages, a need for more robust (higher power) reference drivers, an introduction of floating gate terminals, a need to use thick-oxide devices (resulting in lower speed switching).